A primary focus of the present invention is the field of radio frequency (RF) and microwave power amplifiers capable of use in telecommunication applications. Continuing pressure on the limited spectrum available for radio communication systems is forcing the development of spectrally-efficient linear modulation schemes. Since the envelopes of a number of these linear modulation schemes fluctuate, intermodulation products can be generated in the non-linear power amplifier. This results in the average power being delivered to the antenna being significantly lower than the maximum power, leading to poor efficiency of the power amplifier. Specifically, in this field, there has been a significant amount of research effort in developing high efficiency topologies capable of providing high performances in the ‘back-off’ (linear) region of the power amplifier.
Linear modulation schemes require linear amplification of the modulated signal in order to minimise undesired out-of-band emissions. Quantum processes within a typical RF amplifying device are inherently non-linear by nature. Only when a small portion of the consumed DC power is transformed into RF power, can the transfer function of the amplifying device be approximated by a straight line, i.e. as in an ideal linear amplifier case. This mode of operation provides a low efficiency of DC to RF power conversion, which is unacceptable for portable (subscriber) wireless communication units. Furthermore, the low efficiency is also recognised as being problematic for the base stations.
Furthermore, the emphasis in portable (subscriber) equipment is to increase battery life. The emphasis for base station designers is to reduce operating and equipment cost (power consumption, size, power dissipation, etc.). Hence, such operating efficiencies of the amplifiers used must be maximised. To achieve both linearity and efficiency, so called linearisation techniques are used to improve the linearity of the more efficient amplifier classes, for example class ‘AB’, ‘B’ or ‘C’ amplifiers. A number of linearising techniques exist, which are often used in designing linear transmitters, such as Cartesian Feedback, Feed-forward, and Adaptive Pre-distortion.
A further technique, which is a focus of the present invention, is a ‘Doherty’ amplifier. The concept behind a Doherty amplifier is to increase the efficiency of a power amplifier in the so-called ‘back-off’ region, and was described in the 1930's by Mr Doherty. A way to improve further a ‘Doherty’ amplifier (with regard to efficiency/linearity trade-off) is described in a paper authored by Youngoo Yang, and titled “A microwave Doherty amplifier employing envelope tracking technique for high efficiency and linearity”, IEEE Microwave and Wireless Components Letters, Vol. 13, no 9, September 2003.
A problem with the existing Doherty technique with envelope tracking (or gate bias modulation) is that it inherently requires a delay block at the input of the radio frequency (RF) power amplifier (PA) in all ‘practical’. Such a delay function is very difficult to integrate on an integrated circuit (IC). Furthermore, the delay function often requires tuning implemented as a microstrip line, due to mismatch effects creating efficiency problems at radio frequencies.
Referring now to FIG. 1, a known Doherty Amplifier topology 100 is illustrated. The Doherty Amplifier topology 100 employs a modulated or envelope tracking bias technique, as described in the aforementioned paper authored by Youngoo Yang. An RF input signal 105 is input to a directional coupler 110 and thereafter fed to two distinct amplification paths via a delay line 115. The two amplification paths are substantially ‘matched’, to facilitate their combined non-linear outputs producing a linear RF output signal 195. The two amplification paths comprise RF transmission paths 125, 130 that feed into input pre-matching circuits 145. The two (input) paths are coupled via resistor 135. One amplification path is provided with a carrier bias 150, input to a gate of a first high-power transistor 180. The second amplification path incorporates a λ/4 transmission path (equivalent to a 90 degree phase shift) and is provided with a peaking bias 160 (as described in greater detail below), input to a gate of a second high-power transistor 182.
The two RF power transistors 180, 182 are input to two respective output matching circuits 185 and combined together via a further transmission line 188. The design of the Doherty amplifier is such that the combined output from the two respective amplification paths, which comprise non-linear transistors, are substantially complementary in producing a linear output signal, i.e. the respective delay lines and respective bias signals applied to the transistors are configured to produce a (combined) linear RF output signal 195.
In order to modulate 160 the bias level of the peaking amplifier 182, a portion of the RF input signal 105 is extracted by the coupler 110 and is detected by RF detector 175. The portion of the RF input signal 105 is then buffered 170, and applied to the gate (or base in a bipolar transistor arrangement) of the transistor/peaking amplifier 182, via RF choke 165.
Referring now to FIG. 2, a known circuit 200 for implementing the bias control of the peaking amplifier (say transistor 182 of FIG. 1) is illustrated. Here, the portion of RF input signal 205 is input to a gate and drain port of a field effect transistor (FET) (T1) 210 via a series capacitance. The gate reference voltage is applied via resistor 215. An output matching circuit comprises ‘R1’ 220 and ‘C1’ 225, to couple the emitter port of T1 to a gate port of a second transistor (T2) 235, used as a buffer (emitter-follower). The drain port of T2 235 is provided by Vdd 230 and the emitter port provides an output peaking bias voltage 245, grounded via resistor 240.
Referring back to FIG. 1, the role of the buffer amplifier (often implemented as a video amplifier) 170 is to adjust the level of the detected RF input signal and to deliver sufficient current to the RF output/load 195. In this manner, the buffered (video) signal (as illustrated by waveform 265 in FIG. 2) follows, to some degree, the envelope of the RF input signal 105, 205 (as illustrated by waveform 255 in FIG. 2) without a delay. The load 195, as seen by the buffer 170, comprises the RF power transistor 182 and the surrounding RF components. This load is essentially capacitive.
In order to follow the video signal, the buffer 170 needs to be able to charge and discharge a capacitor at a high speed (up to 20 MHz for a 3rd generation (3G) telecommunication product). A common way to implement the buffer 170 is to use a high-speed commercial video amplifier.
Due to the inherent delay in the video path, it is necessary to add a delay 115 in the RF path, so that the RF signal envelope and the modulated bias control signal are correctly aligned. As would be appreciated by a skilled artisan, the integration of a delay line (or a delay filter) 115 at the input of a high power amplifier 182 is complex. This is a major limitation in the use of such a Doherty amplifier technique in high-volume production.
Thus, a need exists for a wireless communication unit and a power amplifier circuit to drive a low impedance capacitive load, at high speed with minimum delay, which is suitable for implementation in a Doherty amplifier design.